THE SPARQ-2020 CHIPSET SERIES FOR 5G APPLICATIONS
Sparq-2020 System on Chip (SoC)
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First in the Market
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5G 3GPP standard compliant (Rel-15)
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Includes 5G PHY and MAC ( Layers 1 , 2)
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Optimized for URLLC – including “Sparq Minislots“ and integrated mobile edge computing (“I-MEC”)
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FPGA based (16 nm technology)
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Enables customization via API’s
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Main features:
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3 x 200 MHz BW
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> 10 Gbps Capacity (with carrier aggregation)
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Latency < 0.5 msec
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MU-MIMO; Beam Forming, CoMP
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Sparq-2020 System on Chip
Sparq-2020-RDB (Reference Design Board)
Main Features
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Provides an easy and painless process from design to commercial product
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Supports different products within the 5G architecture ( New Radio, RRH, SRRH, etc.)
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Supports different frequencies by external RF boards interfaces
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Large FPGA including 4 ARM cores
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72bits DDR4 SODIMM 4G connected to ARM cores
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64 bits DDR4 to FPGA Logic
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Embedded GPS receiver
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Battery option to GPS receiver, save RTC when power is off
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Programmer clocks chip, support IEEE 1588 synchronization
Interfaces
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FMC connector
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4 x 10G SFP+
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4 x CPRI SFP+ (can be used for Ethernet 10G instead)
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1 x USB to control 4 UARTS: a- for CPU, b-for CPU, c- for FPGA, d- for GPS
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2 x Mictor connectors for debugging
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5 x SMA connectors: a- External 10MHz input, b- External 10MHz output, c- 1pps input, d- 1pps output, e- GPS Antenna
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Additional clock generator chip - Ultra Low-Noise JESD204B Compliant Clock Jitter
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PCIe x 4 Gen2 for external server connection or MEC
Power and Environmental
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Power Inputs: -48V/24V/12 V