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Low latency, high performance

Sparq-2025-SRU - The Fastest 5G Smart Radio Unit

The Sparq-2025-SRU is a component of a unique Distributed Architecture design for a New Radio (NR, 5gNB) designated for 5G infrastructure that fully complies with 3GPP 5G Standards (Rel-15 and Rel-16 ) Optimized for Ultra Reliable Low Latency Communication (URLLC) and supports enhanced Mobile Broadband (eMBB) and Massive Machine type Communication (mMTC).
The Sparq-2025-SRU is based on the RunEL Sparq-2025-3 System on Chip (SoC).

The Sparq-2025-SRU includes substantial innovation enhancing existing state of the art implementations such as: Distributed Architecture with ORAN (option 7.2) PHY split; 3.5GHz Beam Forming Phased Array, the Sparq Minislots, FPGA Based HW Accelerator that reduces the latency in wireless broadband cellular communication to unprecedented records in order to support applications such as: V2X, Remote Surgery, On line Gaming, Automated Factory, Augmented and Virtual Reality, IoT, Tactile Internet, etc

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DOWNLOAD THE BROCHURE

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First in the Market

The first ever technology to use RunEL's Distributed Architecture.

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Include PHY (Physical Layer)

Includes 5G PHY (Layer 1) with PHY split (option 7. x).

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Optimized for URLLC

Including “Sparq Minislots“, Hardware based MAC, Cell-less instantaneous handoffs and integrated mobile edge computing (“I-MEC”).

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5G 3GPP Compliant

Designed for 5G infrastructure that fully complies with the 3GPP Standard.

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Multiple Beam Forming

Includes 28GHz or 3.5 GHz multiple beam steerable Beam Forming Antenna

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Broad Coverage

Large coverage area using up to 64 RRHs with one DRAN

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FPGA

Includes FPGA chip based on 16 nano-meter technology.

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Open and Customizable

Includes an open Architecture that enables customization via API

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Indoor/Outdoor Deployment

Flexible deployment models for indoor and outdoor settings

A Competitive Edge

  • 5G 3GPP standard compliant (Rel-15 and Rel-16)

  •  Includes PHY split (O-RAN option 7. 2)

  • Includes 3.5 GHz multiple Beam Forming Antenna

  • Optimized for URLLC – including “Sparq Minislots“ , FPGA based HW Accelerator.

  • Includes Time of Arrival (ToA) measurement Algorithm for Accurate UE location measurement (1 cm )

  • FPGA chip based on 16 nanometer technology

  • Open Architecture enables customization via API’s

  • Based on the RunEL Sparq-2025-3 SoC

  • Includes network data Harvesting and Mining capability for AI based applications and Digital Twin

  • Flexible deployment scenarios for indoor and outdoor

Full Features List - Sparq-2025-SRU

  •  Includes low PHY in SRU

  •  4 dual polarized beams ( 8 x Tx/Rx Channels)

  •  3.3-3.8 GHz operation Band N78 (other frequency bands are optional including mm Waves)

  •  4 x 100 MHz channel BW (50 and 20 MHz available as well)

  •  23 dBm output power/ beam ( Channel)

  •  Up to 4 Gbps Capacity for RU

  •  Up to 0.5 Gbps Capacity per beam

  •  Physical Layer split between DU and RUs connected via fast Ethernet Ring (10 Gbps) or Hub and Stroke (Star) Architecture (10Gbps)- O-RAN Compliant

  • Latency <0.5 msec

  •  Sub Carrier Spacing- 15, 30, 60, 120, 240 KHz

  •  TTI Spacing – from 8.25 to 1000 msec (TTI Spacing depends on Subcarrier- spacing and number of OFDM symbols)

  •  FDD and Dynamic TDD Supported

  •  CSI-RS, PTRS, DMRS- Supported

  •  PA Blanking for Energy Efficiency

  •  CP-OFDMA implemented in UL and DL and DFT-S-OFDM for UL

  •  Indoor and Outdoor operation

  • 64 bits DDR4 to FPGA Logic

  • Embedded GPS receiver for outdoor synchronization

  • Battery option for GPS receiver, save RTC when power is off

  • Support IEEE 1588synchronization

Download the Brochure

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